Handling node address failure in a distributed nodal system of processors

ABSTRACT

Addressing failure is handled in a nodal system of processor nodes, which comprise at least one processor and at least one interface to a network. Upon detection of a node address failure of a processor node for the network, such as lack of a node address, or presence of a duplicate address, the processor node is disabled from the network, thereby temporarily failing the processor node so that the system remains operational. An alternate node address stored in nonvolatile memory may be selected that avoids the node address failure.

FIELD OF THE INVENTION

This invention relates to distributed nodal systems of processors, and,more particularly, to node addressing in a network of a nodal system ofprocessors. One example of a distributed nodal system of processorsconstitutes processors for operating an automated data storage library.

BACKGROUND OF THE INVENTION

Distributed nodal systems of processors, also called “embedded”processor systems, are being employed in a wide variety of applications,and in ever increasing numbers. In distributed nodal systems ofprocessors, for example, in a control system, overall system control isdistributed among two or more processor nodes in the system or product.

An advantage of such systems is that problem diagnosis and repair issimplified because functions are isolated to different areas of thesystem. Further, such systems can be expanded by adding components andprocessor nodes, without replacing the entire system. The nodes of adistributed control system are usually interconnected with one or morecommunication networks, herein called a “network”.

One example of a control system comprising a distributed nodal system ofprocessors comprises an automated data storage library, such as an IBM3584 Ultra Scalable Tape Library. The processors of the 3584 library areembedded with various components of the library, communicate over a busnetwork, and operate the components and, thereby, the library. Adiscussion of an automated data storage library with a distributed nodalsystem of processors is provided in U. S. Pat. No. 6,356,803, issuedMar. 12, 2002. Repair actions for such systems may comprise replacing anindividual component, a processor node, or a processor at the node. Thelibrary is formed of one or more “frames”, each comprising a set orsubset of library components, such as storage shelves for storing datastorage media; one or more data storage drives for reading and/orwriting data with respect to the data storage media; a robot accessorfor transporting the data storage media between the storage shelves anddata storage drives; a network; and a plurality of processor nodes foroperating the library. The library may be expanded by adding one or moreframes and/or one or more accessors or other nodes.

Another example of a control system comprising a distributed nodalsystem of processors comprises an automobile multi-processor network.

In order to communicate over the network, the components and/or theprocessor nodes, must have node addresses, such as employed with CANbusses or Ethernet networks, as are known to those of skill in the art.When a frame is added, the processor node(s) added to the network mayhave no node address, or have a partial node address, and node addressesmust be given to the new processor nodes. When an individual component,processor node, or a processor at the node, is replaced, either with anew component, etc., or another component, etc., is swapped, theprocessor node may have no node address, or, if swapped, may employ itsprevious node address. Further, processor node cards may beinterchangeable for all of the components, allowing ease of partshandling and to simplify diagnosis and repair, but preventing the use ofstatic addressing where there is a separate part number for each nodeaddress, or preventing the node address from being permanently fixed ateach processor node card.

One way of providing a new node address is for an operator or repairperson to assign a node address. In one example of a complex nodeaddress, a component may have a function portion of an address codedinto a card, and a frame number is supplied to the processor node, andthe function address and frame number are combined to calculate a nodeaddress. Alternatively, automatic modes of providing new node addressesmay be employed. As one example, a cable is designed with certain linestied high or low to provide a binary number that may be employed tocalculate the node address. As another example, as discussed in U.S.patent application Ser. No. 09/854,865, filed May 14, 2001, a pulsegenerator and delay signal generator may provide an automatic framecount, which may be used with the function address to calculate the nodeaddress. As another example, a server may employ a dynamic hostconfiguration protocol (DHCP) to give a processor node an IP address.

In either a manual or an automated mode, failure is a possibility. Forexample, the operator may misjudge the placement or function of theprocessor node. In an automatic mode, the binary cable might becomedefective, misplugged, or the wrong cable might be used. As anotherexample, the frame counter circuit might become defective, or thecabling could become misplugged.

In such a case, the component may have no node address when on thenetwork, may have a wrong address, or may present an address that is aduplicate of another component on the network. A duplicate address ispossible when one processor node is at a component which performs aduplicate function as another component, and misreads the frame number,and employs the erroneous frame number in the address. Alternatively,the processor node may be swapped from one system to another, and be ata different location in the new system. Addressing errors, such as thepresence of an unknown component or duplicate on the network, can renderall or part of the system inoperable, and require maintenance actions.

Failures of products are becoming less tolerable as systems and customerexpectations move toward a concept of continuous availability, such asthe well known “24×7×365” availability.

As an example, automated data storage libraries provide a means forstoring large quantities of data on data storage media that are notpermanently mounted on data storage drives, and that are stored in areadily available form on storage shelves. One or more robot accessorsretrieve selected data storage media from storage shelves and providethem to data storage drives. Typically, data stored on data storagemedia of an automated data storage library, once requested, is neededquickly. Thus, it is desirable that an automated data storage library bemaintained in an operational condition on a continuous basis as much aspossible.

Automated data storage libraries may comprise systems which are operatedby a plurality of processors working together, such as a centralcontroller which interfaces with the host systems through an externalinterface, and provides a constantly updated inventory of the locationsand content of the data storage media within the library, and a robotcontrol system which identifies precise locations of the data storagedrives and the storage shelves, and calculates the best operation of therobot accessor(s) to efficiently transport data storage media betweenthe various storage shelves and data storage drives. Many of thecomponents are redundant, allowing a processor node to fail, and stillhave the overall system operate, but all are dependent upon a propernetwork addressing structure to perform together.

Global addressing is known, for example, as shown by U.S. Pat. No.5,987,506 for allocating addresses across multiple “clouds” by carefullysegmenting the addresses, and does not allow the same address to beallocated in more than one cloud, but provides no method of handlingaddressing failures.

There are many examples of conflicts in addressing. For example, U.S.Pat. No. 5,386,515, resolves a conflict by shifting an address space ofa hardware adapter to a next sequential address space, ignoring theconflicting address space. However, the system is down and notoperational until the conflict is resolved. IBM Technical DisclosureBulleting Vol. 41, No. 01, January, 1998, pp. 703-705, forces a reply bya host in response to duplication of both sender and receiver IPaddresses, so that the duplicate host turns off its interface, and postsa warning message. The replying host may keep using the IP addressesuntil it is corrected manually, reducing the disruption to the replyinghost. When a node logs on, all hosts on the network will receive theduplicate IP addresses, and all may thus go through the reply process.Only after the duplicate host receives the reply and turns off itsinterface, can the replying hosts communicate with the original IPaddress owner.

SUMMARY OF THE INVENTION

In accordance with the present invention, a distributed nodal system ofprocessors, such as of an automated data storage library, a processornode of the system, a method, and computer readable program code, handleaddressing failure for the nodal system.

In one embodiment, a distributed nodal system of processors in a networkare provided, wherein the processor nodes comprise at least oneprocessor and at least one interface to the network. At least one of theprocessor nodes, upon detection of a node address failure of theprocessor node for the network, such as lack of a node address, anominal address that is a wrong address, or comprises a duplicateaddress, for example, detected at the processor node interface, disablesthe processor node from the network. By disabling the processor node orits nominal address from the network, only the processor node and itscomponent are temporarily failed, and the system thus remainsoperational. The node address is for addressing the processor node inthe network upon enabling the processor node in the network.

In another embodiment, the processor node additionally comprises anonvolatile memory, and maintains an alternate node address of theprocessor node in the nonvolatile memory. As an example, the alternatenode address may comprise the node address of the last successfuldetection of node addressing. The processor node, upon detecting a nodeaddress failure, for example, by detecting a conflict, or as anotherexample, by attempting to determine its own node address externally, andfailing to determine any usable node address as its own, selects a nodeaddress that avoids the node address failure, by selecting the alternatenode address in the nonvolatile memory.

In a further embodiment, a processor node initially determines a nominalnode address as its own, senses node addresses of other processor nodesof the network, and compares the sensed node addresses of otherprocessor nodes with the nominal node address. If the processor nodedetermines the existence of any conflict between at least one of thesensed node addresses of other processor nodes with the nominal nodeaddress, the existing conflict comprises a node address failure of theprocessor node for the network, and the processor node is disabled fromthe network.

In a still further embodiment, at least two of the processor nodes ofthe network are subject to reset, and comprise at least one processor,at least one interface to the network, and a timer, the timermaintaining an indication of time since the processor node has beenreset. As above, a node address failure is determined upon the existenceof any conflict between at least one of the sensed node addresses ofother processor nodes with the nominal node address of a processor node.

A processor node having the conflicting node address, compares thetimers, to determine if it has the more recent time since a reset. Ifthe processor node has the more recent time, then its nominal address isdisabled from the network.

In another embodiment, a wrong node address may be determined by theprocessor node maintaining designating information of element(s)associated with the node. In one example, data storage drives coupled toa processor node have unique serial numbers, and the processor nodestores the serial numbers as designating information. When the nodedetermines a nominal node address, it senses the present designatinginformation of associated elements, and compares the present designatinginformation to the maintained designating information. A determinationof a failure of a match is a node address failure of the processor node,resulting in disabling the processor node nominal address from thenetwork.

By disabling a processor node having an address failure from thenetwork, only the component is temporarily failed, and the systemremains operational. Employing an alternate node address which avoidsthe address failure, further prevents any disruption to the system, andavoids any immediate repair action for the processor node or component.

For a fuller understanding of the present invention, reference should bemade to the following detailed description taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an isometric view of an automated data storage library whichmay implement a plurality of processor nodes in accordance with thepresent invention;

FIG. 2 is a block diagrammatic representation of an embodiment of theautomated data storage library of FIG. 1, employing the plurality ofprocesssor nodes in accordance with the present invention;

FIG. 3 is a block diagrammatic representation of a plurality ofprocessor nodes of FIG. 2; and

FIG. 4 is a flow chart depicting embodiments of the method of thepresent invention for handling addressing failure for the processornodes of FIGS. 2 and 3.

DETAILED DESCRIPTION OF THE INVENTION

This invention is described in preferred embodiments in the followingdescription with reference to the Figures, in which like numbersrepresent the same or similar elements. While this invention isdescribed in terms of the best mode for achieving this invention'sobjectives, it will be appreciated by those skilled in the art thatvariations may be accomplished in view of these teachings withoutdeviating from the spirit or scope of the invention.

FIG. 1 illustrates an embodiment of an automated data storage library10, which may implement a plurality of processor nodes in accordancewith the present invention. The library is arranged for accessing datastorage media 14 in response to commands from at least one external hostsystem, and comprises a plurality of storage shelves 16 for storing datastorage media; at least one data storage drive for reading and/orwriting data with respect to the data storage media; and at least onerobot accessor 18 for transporting the data storage media between theplurality of storage shelves 16 and the data storage drive(s). Thelibrary may also comprise an operator panel 23 or other user interface,such as a web-based interface, which allows a user to interact with thelibrary. The library 10 may comprise one or more frames 11-13, eachhaving storage shelves 16 accessible by the robot accessor 18. The robotaccessor 18 comprises a gripper assembly 20 for gripping one or moredata storage media 14, and may include a bar code scanner 22 or readingsystem, such as a smart card reader or similar system, mounted on thegripper 20, to “read” identifying information about the data storagemedia 14.

FIG. 2 illustrates an embodiment of a data storage library 10 of FIG. 1,which employs a plurality of processor nodes in accordance with thepresent invention. An example of a data storage library which mayimplement the present invention is the IBM 3584 Ultra Scalable TapeLibrary. The library comprises a base frame 11, may additionallycomprise one or more extension frames 12, and may comprise a highavailability frame 13.

The base frame 11 of the library 10 comprises one or more data storagedrives 15, and a robot accessor 18. As discussed above, the robotaccessor 18 comprises a gripper assembly 20 and may include a readingsystem 22 to “read” identifying information about the data storage media14. The data storage drives 15, for example, may be optical disk drivesor magnetic tape drives, and the data storage media 14 may compriseoptical or magnetic tape media, respectively, or any other removablemedia and associated drives. As examples, a data storage drive maycomprise an IBM LTO Ultrium Drive, may comprise a DLT 8000 Drive, etc.Additionally, a control port may be provided, which acts to communicatebetween a host and the library, e.g., receiving commands from a host andforwarding the commands to the library, but which is not a data storagedrive.

The extension frame 12 comprises additional storage shelves, and maycomprise additional data storage drives 15. The high availability frame13 may also comprise additional storage shelves and data storage drives15, and comprises a second robot accessor 28, which includes a gripperassembly 30 and may include a bar code scanner 32 or other readingdevice, and an operator panel 280 or other user interface. In the eventof a failure or other unavailability of the robot accessor 18, or itsgripper 20, etc., the second robot accessor 28 may take over.

In the exemplary library, each of the robot accessors 18, 28 moves itsgripper in at least two directions, called the horizontal “X” directionand vertical “Y” direction, to retrieve and grip, or to deliver andrelease the data storage media 14 at the storage shelves 16 and to loadand unload the data storage media at the data storage drives 15.

Referring to FIGS. 2 and 3, the library 10 receives commands from one ormore host systems 40, 41 or 42. The host systems, such as host servers,communicate with the library directly, e.g., on path 80, through one ormore control ports (not shown), or through one or more data storagedrives 15, providing commands to access particular data storage mediaand move the media, for example, between the storage shelves and thedata storage drives. The commands are typically logical commandsidentifying the media and/or logical locations for accessing the media.

The exemplary library is controlled by a distributed control systemreceiving the logical commands from hosts, determining the requiredactions, and converting the actions to physical movements of the robotaccessor 18, 28.

In the exemplary library, the distributed control system comprises aplurality of processor nodes, each having one or more processors. In oneexample of a distributed control system, a communication processor node50 may be located in the base frame 11. The communication processor nodeprovides a communication link for receiving the host commands, eitherdirectly or through the drives 15, via at least one external interface,e.g., coupled to line 80. The communication processor node 50 mayadditionally provide a communication link 70 for communicating with thedata storage drives 15.

The communication processor node 50 may be located in the frame 11,close to the data storage drives 15. Additionally, in an example of adistributed processor system, one or more additional work processornodes are provided, which may comprise, e.g., a work processor node 52that may be located at the robot accessor 18, and that is coupled to thecommunication processor node 50 via a network 60. Each work processornode may respond to received commands that are broadcast to the workprocessor nodes from any communication processor node, and the workprocessor node may also direct the operation of the robot accessor,providing move commands. An XY processor node 55 may be provided and maybe located at an XY system of the robot accessor 18. The XY processornode 55 is coupled to the network 60, and is responsive to the movecommands, operating the XY system to position the gripper 20.

Also, an operator panel processor node 59 may be provided at theoperator panel 23 for providing an interface for communicating betweenthe operator panel and the communication processor node 50, the workprocessor node 52, and the XY processor node 55.

A network comprising a common bus 60 is provided, coupling the variousprocessor nodes. The common bus may comprise a robust wiring network,such as the commercially available “CAN” bus system, which is amulti-drop network, having a standard access protocol and wiringstandards, for example, as defined by CiA, the CAN in AutomationAssociation, Am Weich selgarten 26, D-91058 Erlangen, Germany. Othersimilar bus networks, such as Ethernet, or a wireless network system,such as RF or infrared, may be employed in the library as is known tothose of skill in the art. The processor nodes, e.g., nodes 50, 52, 55and 59 of FIG. 3, may be coupled to the network 60 at a node interface126 a, b, c, d. Herein, the term “network” comprises any communicationmeans between processor nodes which employs node addressing.

Referring to FIG. 2, the communication processor node 50 is coupled toeach of the data storage drives 15 of the base frame 11, via lines 70,communicating with the drives and with host systems 40, 41 and 42.Alternatively, the host systems may be directly coupled to thecommunication processor node 50 at input 80, or to control port devices(not shown) which connect the library to the host system(s) with alibrary interface similar to the drive/library interface. As is known tothose of skill in the art, various communication arrangements may beemployed for communication with the hosts and with the data storagedrives. In the example of FIG. 2, host connections 80 and 81 are SCSIbusses. Bus 82 comprises an example of a Fibre Channel-Arbitrated Loopwhich is a high speed serial data interface, allowing transmission overgreater distances than the SCSI bus systems.

The data storage drives 15 may be in close proximity to thecommunication processor node 50, and may employ a short distancecommunication scheme, such as SCSI, or a serial connection, such asRS-422. The data storage drives 15 are thus individually coupled to thecommunication processor node 50 by means of lines 70.

An extension frame 12 may be provided, and may be coupled by anextension common bus 152, into the network 152, 60. Anothercommunication processor node 155, similar to communication processornode 50 of FIG. 3, may be located in the extension frame and maycommunicate with hosts, e.g., at input 156, and data storage drives 15in extension frame 12, e.g., via lines 170. The communication processornode 155 is coupled to the network 152, 60 at a node interface similarto node interface 126 a of FIG. 3, the communication processor node 155providing a communication link for the commands to the network 152, 60so that the commands are linked to the base frame work processor node52.

The communication processor node 155 may be mounted in the extensionframe 12, closely adjacent to the coupled data storage drives 15 of theextension frame 12, communicating with the drives and with the attachedhost systems. The data storage drives 15 are also individually coupledto the communication processor node 155 by means of lines 170.

Additional extension frames with identical communication processor nodes155, storage shelves 16, data storage drives 15, and extension busses152, may be provided and each is coupled to the adjacent extensionframe.

Further, the data storage library 10 may additionally comprise anotherrobot accessor 28, for example, in a high availability frame 13. Therobot accessor 28 may comprise a gripper 30 for accessing the datastorage media, and an XY system 255 for moving the robot accessor. Thehigh availability frame may be adjacent an extension frame 12, oradjacent the base frame 11, and the robot accessor 28 may run on thesame horizontal mechanical path as robot accessor 18, or on an adjacentpath. The exemplary control system additionally comprises an extensioncommon bus 200 forming a network coupled to network 152 of an extensionframe or to the network 60 of the base frame. Another communicationprocessor node 250 may be provided, which is also similar tocommunication processor node 50, and may be located in the highavailability frame 13, for receiving commands from hosts, eitherdirectly at input 256, or through control ports (not shown), or throughthe data storage drives 15 and lines 270, e.g., at input 256. Thecommunication processor node 250 is coupled to the high availabilityframe network 200 and provides a communication link to the network,e.g., at a node interface similar to interface 126 a of FIG. 3.

The communication processor node 250 may be mounted closely adjacent tothe coupled data storage drives 15 of the high availability frame 13,communicating with the drives and with the attached host systems. Thedata storage drives 15 are also individually coupled to thecommunication processor node 250 by means of lines 270, and using aninterface such as RS-422.

Referring to FIG. 2, a computer program implementing the presentinvention may be provided at one of the processor nodes, e.g., at workprocessor 52, or, optionally at processor 50, processor 155, orprocessor 250, or may be implemented in a plurality, or all, of theprocessor nodes.

Another example of a control system comprising a distributed nodalsystem of processors comprises an automobile multi-processor network.

Referring to FIG. 3, the processor nodes 50, 52, 55 and 59 comprise aprocessor 122 a, b, c, d, which may comprise any microprocessor deviceknown in the art. The processor 122 a, b, c, d, operates under thecontrol of program code, often called “firmware”, since the code isrelated to the hardware constituting the library, as discussed above.The firmware is such that the processors operate the components of thesystem, e.g., shown as nodal hardware 132, 134, 136, 138. The firmwareis typically maintained in a nonvolatile programmable memory 124 a, b,c, d. The nonvolatile memory 124 a, b, c, d may comprise any nonvolatilememory device known in the art, such as a flash memory, read only memory(ROM), electrically erasable programmable read only memory (EEPROM),battery backed-up RAM, hard disk drive etc. Alternatively, thenonvolatile memory 124 a, b, c, d may be located in processor 122 a, b,c, d, respectively.

The firmware program code image may be the same for all of the processornodes, having both common code and specific code for each of the variousfunctions, but which specific code is only used by the processor of thespecific function. Alternatively, different code images may be providedfor each of the processor nodes, specifically incorporating only coderequired by the processor of the specific function.

In order to communicate over the network, the processor nodes, have nodeaddresses. As discussed above, node addresses, such as employed with CANbusses or Ethernet networks, as are known to those of skill in the art.In the example of a library, when a frame is added, the processor nodesadded to the network may have no node address, and node addresses mustbe given to the new processor nodes. In addition, when an individualcomponent, processor node, or a processor at the node, is replaced,either with a new component, etc., or another component, etc., isswapped, the processor node may have no node address, or, may employ itsprevious node address from another node position or another library.Incorrect node addressing may be detected by comparing saved library orframe unique information, as will be discussed hereinafter.

One way of providing a new node address is for an operator to assign anode address. In one example of a complex node address, a component mayhave a function portion of an address coded into a card, and a framenumber is supplied to the processor node, and the function address andframe number are combined to calculate a node address. As an example,frames may be numbered consecutively, as “01”, “02”, etc., and eachfunction could be given a different number. For example, a communicationprocessor node designation of “C” in hex, and a frame number of “2”,could have an address of “xC2”. Alternatively, automatic modes ofproviding new node addresses may be employed. As one example, a cable isdesigned with certain lines tied high or low to provide a binary numberthat may be employed to calculate the node address. As another example,as discussed in U.S. patent application Ser. No. 09/854,865, filed May14, 2001, a pulse generator and delay signal generator may provide anautomatic frame count, to determine the number of the frame, such as“01”, “02”, as above. The automatic frame count may be used with thefunction address to calculate the node address. As another example, aserver may employ a dynamic host configuration protocol (DHCP) to give aprocessor node an address.

As discussed above, failure is a possibility. As an example, theoperator may misjudge the placement or function of the processor node.In the automatic mode, the binary cable might become defective,misplugged, or the wrong cable might be used. As another example, theframe counter circuit might become defective, or the cabling couldbecome misplugged.

In such a case, the component may have no usable node address when onthe network, may have a wrong address, or may present an address that isa duplicate of another component on the network. A duplicate address ispossible when one processor node is at a component which performs aduplicate function as another component, and misreads the frame number,and employs the erroneous frame number in the address. Alternatively,the processor node may be swapped from one system to another, and be ata different location in the new system. Addressing errors, such as thepresence of an unknown component, or a component with the wrong address,or duplicate on the network, can render all or part of the systeminoperable, and require maintenance actions.

Referring additionally to FIG. 4, in one embodiment, upon detection of anode address failure of a processor node for the network, such as lackof a node address, or presence of a duplicate address, for example,detected at the processor node interface, the processor node, or thesystem, (1) disables the processor node from the network, and/or (2)selects a node address that avoids the node address failure. Theselected node address is for addressing the processor node in thenetwork upon enabling the processor node in the network.

The process begins at step 190. In step 201, a processor node, such asprocessor node 50 of FIGS. 2 and 3, senses the network, e.g., network60, at node interface 126 a. As an example, the processor node may bepowered up, be swapped into position, be in a frame that is added to thenetwork, or have been reset, for example, because the processor 122 aand/or another component of the node have been upgraded. As an example,the processor node contains a firmware or hardware power-on counterwhich starts the process of enabling the processor node. Once certaininternal aspects are conducted, the processor node conducts step 201. Asan alternative, as soon as the processor node comes up, a signal isprovided on a non-disruptive basis, to a master node, for example, bymeans of a signal on a line, and the master node conducts step 201 forthe processor node, e.g., processor node 50.

Included in step 201 is a check for a node address for the processornode, e.g., processor node 50. As discussed above, an address may beindicated by coding of a cable, by receipt of a manually generated orautomatic indication, etc., and used directly or combined with internalinformation to determine a node address.

Step 203 comprises the determination whether any usable node address canbe generated as the result of sensing the network. For example, anunusable address might be the result of a binary cable becomingdefective and having a missing bit, presenting an incomplete address, ormight have a crossed bit, presenting an erroneous or invalid address.Further, the cable may be misplugged, or the wrong cable might be used.As another example, the frame counter circuit might become defective, orthe cabling could become misplugged. An unusable address may alsotherefore comprise no address signal.

Hence, an unusable address, as the term is employed herein, comprises anincomplete address, an erroneous or invalid address, or no addressinformation. A potentially conflicting address may not be usable in anetwork, but is specifically discussed hereinafter. If no usable addresscan be generated, in step 205, the processor node 50 attempts todetermine its node address internally. As one example, a functionportion of the address is encoded in the card, and the remaining portionof an address encoded in a nonvolatile memory, for example, comprising alast successfully known address. In accordance with the presentinvention, in step 206, an alternate node address is read from itsnonvolatile memory 124 a, as is discussed in more detail hereinafterwith respect to step 220. Alternatively, a predetermined node addressmay be provided.

In step 205, a determination is made whether a node address can bedetermined internally. If not, there is no nominal node address, andthere is a node address failure, as indicated by step 207, and theprocessor node is disabled from the network in step 208.

By disabling a processor node having an address failure from thenetwork, only the component is temporarily failed, and the system thusremains operational.

Alternatively, if steps 205 and 206 generate a node address, step 207may be omitted, and any problem with the internally generated addressmay be caught later, e.g., at step 222 as will be discussed. Stillfurther, steps 205, 206 and 207 may be omitted. In this case, a “NO”answer in step 203 would lead directly to step 208.

If a node address can be determined for the processor node, as indicatedby either step 203 or step 205, that address is initially determined instep 210, and, herein, is termed a “nominal” node address. This is todifferentiate the initially determined node address from a node addressthat will actually be used once a check is made for validity or anyconflict, other types of addressing failure discussed hereinafter. Eachof the process steps may be conducted by the processor node itself, orthe system may conduct the process, for example, by a master node.

In step 207, optionally, a determination is made whether the nominalnode address is likely to be valid or is likely to be wrong. Forexample, the nominal node address may be complete, and be in a frame ornetwork location with an apparently correct number, but is in adifferent location within the frame and/or perform a different function,or is in a different library or network.

In accordance with an embodiment of the present invention, a test for avalid node address may comprise querying an associated element, orelements, such as nodal hardware, that has unique identifyinginformation, such as a serial number that can be accessed by the node,and comparing it to a copy of the unique identifying information kept inthe local nonvolatile memory of the node.

Herein, information identifying, defining, or designating hardware orother elements associated with a processor node, is termed “designatinginformation” of associated elements, etc.

Thus, in the example of a library with data storage drives assigned tothe frame of the node, the frame is known to contain a drive or drives,each with a given unique serial number for the “designating information”comparison.

As an example, referring to FIG. 2, the communication processor node 50could query one or more data storage drives 15 over lines 70 and obtainone or more serial numbers, and compare it (them) to the serialnumber(s) stored in nonvolatile memory. If there is a complete match,the assumption can be made that the nominal node address is valid. Moreprecisely, the node contains a correlation between a stored node addressand stored designating information. Since a drive 15 can also beswapped, an inability to make a complete match may not indicate aninvalid node address. Hence, all the component identifiers forcomponents associated with a node may be stored in the node nonvolatilememory as designating information, and a voting scheme employed todetermine whether a sufficient comparison is made to constitute a match.

Alternatively, the node itself may contain designating information, suchas a “MAC” address, or a world-wide name (WWN), or a card serial numberassociated with the node card, that is readable through firmware.

If no match is made, step 207 determines that there is a node addressfailure, and the process proceeds to step 222 and the processor nodenominal node address is disabled from the network at the processor nodeinterface.

If the nominal node address appears valid, the node addresses of otherprocessor nodes of the network, e.g., network 60, 152, 200 of FIG. 2,are sensed in step 212, for example, through alternate communicationmeans, such as an RS-232 connection, or by network broadcasts.Specifically, a node may broadcast “I am ‘C2’, is anyone else”, and willreceive a response if there is a conflict. Then, in step 215, the sensednode addresses of other processor nodes are compared with the nominalnode address. If, in step 216, no conflict is found, the nominal nodeaddress will be used as the node address for the processor node, and theprocess proceeds to step 240, as will be discussed.

If, instead, in step 216, the processor node or system determines theexistence of any conflict between at least one of the sensed nodeaddresses of other processor nodes with the nominal node address, theexisting conflict may comprise a node address failure of the processornode for the network. The processor node, or nodes, having theconflicting node address may optionally be alerted in step 221, forexample, by means of a network broadcast, etc.

As a further embodiment in accordance with the present invention, in theevent of a conflict of node addresses, a further test may be conducted,as will be explained with respect to step 235; otherwise, if the furthertest is not implemented, a node address failure is indicated in optionalstep 222, and the processor node is disabled from the network.

In the further embodiment, at least two of the processor nodes of thenetwork are subject to reset, and comprise at least one processor, atleast one interface to the network, and a timer, the timer maintainingan indication of time since the processor node has been reset. The timeris illustrated only as a firmware timer of the processor, e.g.,processors 122 a, b, c, d, respectively, of processor nodes 50, 52, 55and 59, but may alternatively comprise a hardware timer, as discussedabove. The timers may comprise power-up counters, which are activated orreset at power-up of the processor node. Thus, the timers provide anindication of the time that a processor node has been active. The timersmay comprise large value counters that are unlikely to wrap back to avalue of zero, or may stop counting once a maximum value is reached,since the check is likely to be performed close to reset time of one ofthe processor nodes. The resolution of the timers is not very important,since they are only intended to identify a significant difference.Alternatively, the timers may not begin to count at power-on, butinstead be reset upon determining that the processor node has anon-conflicting address, as will be explained. In such case, the timewill be zero at a newly reset processor node until any conflict isresolved. Thus, a processor node having the more recent time is likelyto have recently been reset, and to have the new conflicting nominaladdress, and a processor node not having the more recent time is likelyto have been successfully operating at the address that is nowconflicting. As above, a node address failure is determined upon theexistence of any conflict between at least one of the sensed nodeaddresses of other processor nodes with the nominal node address of aprocessor node. The processing node determining the node addressfailure, optionally, in step 221, may alert the other processor nodehaving the conflicting sensed node address, of the conflict, forexample, by means of a broadcast, etc., as discussed above.

Step 221 is optional in that a newly reset node is likely to have themore recent time and therefore is also likely to request information ofa conflict. Another node having a conflicting address is likely to havebeen operating successfully, and may only supply the response that ithas the requested address, and does not need to know that there is aconflict. The responding node, however, may also supply its timer valueas part of the response. Hence, the requesting node will have both theresponse from which to determine the existence of an address conflict,and will have the timer value for a comparison. Alternatively, theresponse may first be supplied, and, only after a requesting nodedetermines that there is a conflict, the node separately requests thetimer value.

The processor node and the other processor node having the conflictingnode addresses, as illustrated by step 225, or the system, in step 227,compare the times of the timers, to determine, in step 228, theprocessor node having the more recent time since a reset. A wide band oftime may be considered a tie and not resolve the conflict, in that iftwo nodes are reset and come up with conflicting nominal addresses, a“race” condition may resolve the conflict incorrectly. Hence, an errorsituation may exist and require external inspection to resolve. Thus,herein, a “more recent time” includes a tie.

Alternatively, steps 221 and 225 may be omitted. Steps 227 and 228 maybe performed in response to a broadcast of intent to assign an address.Further, steps 227 and 228 may be performed only by a node that has notyet assigned a node address, since this check is intended to cancel thelater conflicting node from coming up. A node that has been operatingsuccessfully may not consider the possibility of a change of address.

If, in step 228, the processor node is determined to not have the morerecent time, the nominal node address or the node address being used bythe processor node, will be used as the node address for the processornode, and the process proceeds to step 240, as will be discussed.

The processor node having the more recent time as determined in step 228may indicate a node address failure in step 222, causing the processornode to be disabled from the network.

In another embodiment of the present invention, the processor node,e.g., processor node 50 of FIG. 3, additionally comprises a nonvolatilememory 124 a, and maintains an alternate node address of the processornode in the nonvolatile memory. As an example, the alternate nodeaddress may comprise the node address of the last successful detectionof node addressing, as will be discussed with respect to step 220.Alternatively, the system maintains a nonvolatile memory at a knownlocation, for example, at a master node, such as nonvolatile memory 124c of a master node 55.

Step 222 may be a temporary disabling of the processor node while theremaining steps are conducted, or, alternatively, step 222 may beomitted, and the remaining steps conducted first, and any node addressfailure conducted at step 208, as will be discussed.

Thus, upon detecting a node address failure, for example, in step 228,or directly as a result of a conflict, for example, in step 216, thealternate node address in a nonvolatile memory is read in step 235. Thealternate node address comprises an address that is likely to avoid aconflict, such as is determined in step 220. The nonvolatile memory ofstep 235 may be the same or different than the nonvolatile memory ofstep 206, and the alternate node address may be different than the nodeaddress of step 206. If an alternate node address is provided, the nodemay be selected by use of other node identifying information asdiscussed above.

In step 220, the alternate node address of step 235, or the alternateaddress that becomes the nominal node address of step 206, if validatedin step 240, discussed hereinafter, comprises the node address of thelast successful detection of node addressing. For example, when aprocessor node goes through the process of reset and is found to have anode address that avoids conflict with any processor node of thenetwork, that node address is, at least at that point, known to be agood node address. Therefore, in step 220, the known good node addressis stored in the nonvolatile memory of the processor node.

If the processor node is swapped, etc., the once good node address mayconflict in the new environment. Hence, in step 237, the sensed nodeaddresses of the other processor nodes of step 212 are compared to thealternate node address of the nonvolatile memory. Alternatively, steps212 and 215 may be repeated, or similar steps taken. If, in step 238,the alternate node address avoids conflict with the sensed nodeaddresses of the other processor nodes of step 215, and/or passes adesignating information match test of step 207, the alternate nodeaddress avoids a node address failure, and the alternate node address ofthe nonvolatile memory is selected as the node address of the processornode, and the process proceeds to step 240.

If, however, a conflict still, or again, exists, the processor nodepresents an address failure for the network, and, in step 208, isdisabled from the network.

By disabling a processor node having an address failure from thenetwork, only the component is temporarily failed, and the systemremains operational. Employing an alternate node address which avoidsthe address failure, further prevents any disruption to the system, andavoids an immediate repair action for the processor node or component.

In step 240, the processor node is enabled in the network with theapparently valid and non-conflicting address. In step 220, that nodeaddress is stored in the non-volatile memory as an alternate nodeaddress, and the timer may be reset.

It is possible that the resultant nominal node address or alternativenode address, although apparently valid, and non-conflicting, is stillincorrect. Hence, the storing operation of step 220 may additionallyoccur after a further verification, for example, a configuration, etc.Thus there is an added assurance that the address stored in non-volatilememory as backup is a known “good” node address.

In step 220, in addition to storing the now “good” node address in thenonvolatile memory as an alternate node address, the timer may be resetat this time, as discussed above, if the timer is not a power-up timer.

As an alternative, step 240 may be conducted after step 220, such thatthe processor node is enabled in the network with the non-conflictingnode address and step 240 does not comprise additional verification.

Those of skill in the art will understand that the above steps may bemodified and/or changed in sequence from those shown in FIG. 4. Those ofskill in the art will also understand that other, equivalent elementsmay be substituted for those illustrated in FIGS. 1-3, and that theinvention may be implemented in accordance with FIG. 3, in alternativeenvironments than that of the library of FIGS. 1 and 2, one examplecomprising processing nodes of an automobile multi-processor network.

While the preferred embodiments of the present invention have beenillustrated in detail, it should be apparent that modifications andadaptations to those embodiments may occur to one skilled in the artwithout departing from the scope of the present invention as set forthin the following claims.

1. A distributed nodal system of processors, comprising: a network; anda plurality of processor nodes comprising nodes of said network, each ofsaid plurality of processor nodes comprising at least one processor andat least one interface to said network; at least one of said pluralityof processor nodes: upon detection of a node address failure of saidprocessor node for said network, disables said processor node from saidnetwork at said at least one interface.
 2. The distributed nodal systemof processors of claim 1, wherein said at least one processor node:additionally comprises a nonvolatile memory; maintains an alternate nodeaddress of said processor node in said nonvolatile memory; detects saidnode address failure, by attempting to determine its own node address;and failing to determine any usable node address as its own, selectssaid alternate node address in said nonvolatile memory.
 3. Thedistributed nodal system of processors of claim 1, wherein said at leastone processor node detects said node address failure, by sensing saidnetwork at said at least one interface.
 4. A distributed nodal system ofprocessors, comprising: a network; and a plurality of processor nodescomprising nodes of said network, each of said plurality of processornodes comprising at least one processor and at least one interface tosaid network; at least one of said plurality of processor nodes:determines a nominal node address as its own; senses node addresses ofother processor nodes of said network; compares said sensed nodeaddresses of other processor nodes with said nominal node address;determines existence of any conflict between at least one of said sensednode addresses of other processor nodes with said nominal node address,said existing conflict comprising a node address failure of saidprocessor node for said network; and upon detection of said node addressfailure of said processor node for said network, disables said processornode nominal node address from said network at said at least oneinterface.
 5. The distributed nodal system of processors of claim 4,wherein said at least one processor node: upon detection of said nodeaddress failure of said processor node for said network, additionallyselects a node address that avoids said node address failure, saidselected node address for addressing said processor node in said networkat said at least one interface upon enabling said processor node in saidnetwork.
 6. The distributed nodal system of processors of claim 5,wherein said at least one processor node: additionally comprises anonvolatile memory; maintains an alternate node address of saidprocessor node in said nonvolatile memory; upon said determination of aconflict and detection of said node address failure of said processornode for said network, further compares said alternate node address ofsaid nonvolatile memory with said sensed node addresses of said otherprocessor nodes; and if said alternate node address avoids conflict withsaid sensed node addresses of said other processor nodes, selects saidnode address that avoids said node address failure, by selecting saidalternate node address of said nonvolatile memory.
 7. A distributednodal system of processors, comprising: a network; and a plurality ofprocessor nodes comprising nodes of said network, at least two of saidplurality of processor nodes subject to reset, and comprising at leastone processor, at least one interface to said network, and a timer, saidtimer maintaining an indication of time since said processor node hasbeen reset; (I) at least one of said plurality of processor nodes:determines a nominal node address as its own; senses node addresses ofother processor nodes of said network; compares said sensed nodeaddresses of other processor nodes with said nominal node address;determines existence of any conflict between at least one of said sensednode addresses of other processor nodes with said nominal node address,said existing conflict comprising a node address failure in saidnetwork; and (II) said processor node having said conflicting sensednode address: compares the time of said timer of said processor node tothe time of said timer of said other processor node having saidconflicting said sensed node address, to determine the processor nodehaving the more recent time of said timers; and if said processor nodehas said more recent time, disables said processor node nominal nodeaddress from said network at said at least one interface.
 8. Thedistributed nodal system of processors of claim 7, wherein saidprocessor node having said more recent time: additionally selects a nodeaddress that avoids said node address failure, said selected nodeaddress for addressing said processor node having said more recent time,in said network, upon enabling said processor node in said network. 9.The distributed nodal system of processors of claim 8, wherein saidprocessor node having said more recent time: additionally comprises anonvolatile memory; maintains an alternate node address of saidprocessor node in said nonvolatile memory; further compares saidalternate node address of said nonvolatile memory with said sensed nodeaddresses of said other processor nodes; and if said alternate nodeaddress avoids conflict with said sensed node addresses of said otherprocessor nodes, selects said node address that avoids said node addressfailure, by selecting said alternate node address of said nonvolatilememory.
 10. A processor node for a distributed nodal system ofprocessors, said system comprising a network and a plurality ofprocessor nodes, said processor node comprising: at least one interfaceto said network; and at least one processor, said at least oneprocessor: upon detection of a node address failure of said processornode for said network, disables said processor node from said network atsaid at least one interface.
 11. The processor node of claim 10,additionally comprising a nonvolatile memory; and wherein said at leastone processor: maintains an alternate node address of said processornode in said nonvolatile memory; detects said node address failure, byattempting to determine its own node address; and upon failing todetermine any usable node address as its own, selects said alternatenode address in said nonvolatile memory.
 12. The processor node of claim10, wherein said at least one processor detects said node addressfailure, by sensing said network at said at least one interface.
 13. Aprocessor node for a distributed nodal system of processors, said systemcomprising a network and a plurality of processor nodes, said processornode comprising: at least one interface to said network; and at leastone processor, said at least one processor: determines a nominal nodeaddress as its own; senses node addresses of other processor nodes ofsaid network; compares said sensed node addresses of other processornodes with said nominal node address; determines existence of anyconflict between at least one of said sensed node addresses of otherprocessor nodes with said nominal node address, said existing conflictcomprising a node address failure of said processor node for saidnetwork; and upon detection of said node address failure of saidprocessor node for said network, disables said processor node nominalnode address from said network at said at least one interface.
 14. Theprocessor node of claim 13, wherein said at least one processor: upondetection of said node address failure of said processor node for saidnetwork, additionally selects a node address that avoids said nodeaddress failure, said selected node address for addressing saidprocessor node in said network at said at least one interface uponenabling said processor node in said network.
 15. The processor node ofclaim 14, additionally comprising a nonvolatile memory; and wherein saidat least one processor: maintains an alternate node address of saidprocessor node in said nonvolatile memory; upon said determination of aconflict and detection of said node address failure of said processornode for said network, further compares said alternate node address ofsaid nonvolatile memory with said sensed node addresses of said otherprocessor nodes; and if said alternate node address avoids conflict withsaid sensed node addresses of said other processor nodes, selects saidnode address that avoids said node address failure, by selecting saidalternate node address of said nonvolatile memory.
 16. A processor nodefor a distributed nodal system of processors, said system comprising anetwork and a plurality of processor nodes, at least two of saidplurality of processor nodes subject to reset, said processor nodecomprising one of said plurality of processor nodes subject to reset: atleast one interface to said network; a timer, said timer maintaining anindication of time since said processor node has been reset; and atleast one processor, said at least one processor: determines a nominalnode address as its own; senses node addresses of other processor nodesof said network; compares said sensed node addresses of other processornodes with said nominal node address; determines existence of anyconflict between at least one of said sensed node addresses of otherprocessor nodes with said nominal node address, said existing conflictcomprising a node address failure in said network; and compares the timeof said timer of said processor node to the time of said timer of saidother processor node having said conflicting said sensed node address,to determine the processor node having the more recent time of saidtimers; and if said processor node has said more recent time, disablessaid processor node nominal node address from said network at said atleast one interface.
 17. The processor node of claim 16, wherein said atleast one processor, upon said processor node having said more recenttime: additionally selects a node address that avoids said node addressfailure, said selected node address for addressing said processor nodehaving said more recent time, in said network, upon enabling saidprocessor node in said network.
 18. The processor node of claim 17,additionally comprising a nonvolatile memory; and wherein said at leastone processor maintains an alternate node address of said processor nodein said nonvolatile memory; and upon said processor node having saidmore recent time, further compares said alternate node address of saidnonvolatile memory with said sensed node addresses of said otherprocessor nodes; and if said alternate node address avoids conflict withsaid sensed node addresses of said other processor nodes, selects saidnode address that avoids said node address failure, by selecting saidalternate node address of said nonvolatile memory. 19-36. (canceled) 37.A computer program product of a computer readable medium usable with aprogrammable computer, said computer program product having computerreadable program code embodied therein for handling addressing failureof a nodal system of processors, said nodal system comprising a network;and a plurality of processor nodes comprising nodes of said network,each of said plurality of processor nodes comprising at least oneprocessor and at least one interface to said network; said computerprogram product comprising: computer readable program code which causessaid at least one processor of at least one of said processor nodes, todetect a node address failure of said processor node for said network;and computer readable program code which causes said at least oneprocessor of said processor node, to, upon detecting said node addressfailure, disable said processor node from said network at said at leastone interface.
 38. The computer program product of claim 37, whereinsaid processor node additionally comprises a nonvolatile memory; andwherein said computer program product additionally comprises: computerreadable program code which causes said at least one processor of saidprocessor node to maintain an alternate node address of said processornode in said nonvolatile memory; said computer readable program codewhich causes said at least one processor of said processor node todetect said node address failure, comprises causing said at least oneprocessor of said processor node to attempt to determine its own nodeaddress; and said computer readable program code which causes said atleast one processor of said processor node to, upon failing to determineany usable node address as its own, to select said alternate nodeaddress in said nonvolatile memory.
 39. The computer program product ofclaim 37, wherein said computer readable program code which causes saidat least one processor of said processor node to detect said nodeaddress failure, comprises causing said at least one processor of saidprocessor node to sense said network at said processor node interface.40. A computer program product of a computer readable medium usable witha programmable computer, said computer program product having computerreadable program code embodied therein for handling addressing failureof a nodal system of processors, said nodal system comprising a network;and a plurality of processor nodes comprising nodes of said network,each of said plurality of processor nodes comprising at least oneprocessor and at least one interface to said network; said computerprogram product comprising: computer readable program code which causessaid at least one processor of at least one of said processor nodes, todetermine a nominal node address as its own; computer readable programcode which causes said at least one processor of said processor node, tosense node addresses of other processor nodes of said network; computerreadable program code which causes said at least one processor of saidprocessor node, to compare said sensed node addresses of other processornodes with said nominal node address; computer readable program codewhich causes said at least one processor of said processor node, todetermine existence of any conflict between at least one of said sensednode addresses of other processor nodes with said nominal node address,said existing conflict comprising a node address failure of saidprocessor node for said network; and computer readable program codewhich causes said at least one processor of said processor node, to,upon detection of said node address failure of said processor node forsaid network, disable said processor node nominal node address from saidnetwork at said at least one interface.
 41. The computer program productof claim 40, wherein said computer program product additionallycomprises: computer readable program code which causes said at least oneprocessor of said processor node, to, upon detection of said nodeaddress failure of said processor node for said network, select a nodeaddress that avoids said node address failure, said selected nodeaddress for addressing said processor node in said network upon enablingsaid processor node in said network.
 42. The computer program product ofclaim 41, wherein said processor node additionally comprises anonvolatile memory; and said computer program product: additionallycomprises computer readable program code which causes said at least oneprocessor of said processor node, to maintain an alternate node addressof said processor node in said nonvolatile memory; said computerreadable program code which causes said at least one processor of saidprocessor node to select a node address that avoids said node addressfailure, comprises causing said at least one processor of said processornode: to compare said alternate node address of said nonvolatile memorywith said sensed node addresses of said other processor nodes; and ifsaid alternate node address avoids conflict with said sensed nodeaddresses of said other processor nodes, to select said node addressthat avoids said node address failure, by selecting said alternate nodeaddress of said nonvolatile memory.
 43. A computer program product of acomputer readable medium usable with a programmable computer, saidcomputer program product having computer readable program code embodiedtherein for handling addressing failure of a nodal system of processors,said nodal system comprising a network; and a plurality of processornodes comprising nodes of said network, at least two of said pluralityof processor nodes subject to reset, and comprising at least oneprocessor, at least one interface to said network, and a timer, saidtimer maintaining an indication of time since said processor node hasbeen reset; said computer program product comprising: computer readableprogram code which causes said at least one processor of at least one ofsaid processor nodes, to determine a nominal node address of saidprocessor node; computer readable program code which causes said atleast one processor of said processor node, to sense node addresses ofother processor nodes of said network; computer readable program codewhich causes said at least one processor of said processor node, tocompare said sensed node addresses of other processor nodes with saidnominal node address of said processor node; computer readable programcode which causes said at least one processor of said processor node, todetermine existence of any conflict between at least one of said sensednode addresses of other processor nodes with said nominal node addressof said processor node, said existing conflict comprising a node addressfailure in said network; computer readable program code which causessaid at least one processor of said processor node, to compare the timeof said timer of said processor node having said nominal node address tothe time of said timer of said other processor node having saidconflicting said sensed node address, to determine the processor nodehaving the more recent time of said timers; and computer readableprogram code which causes said at least one processor of said processornode, to, if said processor node is determined to have said more recenttime of said timers, disable said processor node nominal node addressfrom said network at said at least one interface.
 44. The computerprogram product of claim 43, wherein said computer program productadditionally comprises: computer readable program code which causes saidat least one processor of said processor node, to, if said processornode is determined to have said more recent time of said timers, selecta node address that avoids said node address failure, said selected nodeaddress for addressing said processor node in said network upon enablingsaid processor node in said network.
 45. The computer program product ofclaim 44, wherein said processor node additionally comprises anonvolatile memory; and said computer program product: additionallycomprises computer readable program code which causes said at least oneprocessor of said processor node, to maintain an alternate node addressof said processor node in said nonvolatile memory; said computerreadable program code which causes said at least one processor of saidprocessor node having said more recent time to select a node addressthat avoids said node address failure, comprises causing said at leastone processor of said processor node: to further compare said alternatenode address of said nonvolatile memory with said sensed node addressesof said other processor nodes; and if said alternate node address avoidsconflict with said sensed node addresses of said other processor nodes,to select said node address that avoids said node address failure, byselecting said alternate node address of said nonvolatile memory. 46.(cancel)
 47. A processor node for a distributed nodal system ofprocessors, said system comprising a network and a plurality ofprocessor nodes, said processor node associated with at least oneelement, said processor node comprising: at least one interface to saidnetwork; and at least one processor, said at least one processor:maintains designating information of said at least one elementassociated with said processor node; determines a nominal node addressas an address for said processor node for said network; senses presentdesignating information of at least one element associated with saidprocessor node; compares said present designating information to saidmaintained designating information; determines whether a match is madebetween said compared said present designating information and saidmaintained designating information, a failure of said match comprising anode address failure of said processor node for said network; and uponsaid node address failure of said processor node for said network,disables said processor node nominal node address from said network atsaid at least one interface.
 48. A method for determining and handlingaddressing failure of a processor node of a distributed nodal system ofprocessors, said system comprising a network and a plurality ofprocessor nodes, at least one of said plurality of processor nodesassociated with at least one element, said at least one processor nodecomprising at least one processor and at least one interface to saidnetwork; said method comprising the steps of maintaining designatinginformation of said at least one element associated with said processornode; determining a nominal node address as an address for saidprocessor node for said network; sensing present designating informationof at least one element associated with said processor node; comparingsaid present designating information to said maintained designatinginformation; determining whether a match is made between said comparedsaid present designating information and said maintained designatinginformation, a failure of said match comprising a node address failureof said processor node for said network; and upon said node addressfailure of said processor node for said network, disabling saidprocessor node nominal node address from said network at said at leastone interface.
 49. A computer program product of a computer readablemedium usable with a programmable computer, said computer programproduct having computer readable program code embodied therein fordetermining and handling addressing failure of a nodal system ofprocessors, said nodal system comprising a network; and a plurality ofprocessor nodes comprising nodes of said network, at least one of saidplurality of processor nodes associated with at least one element, saidat least one processor node comprising at least one processor and atleast one interface to said network; said computer program productcomprising: computer readable program code which causes said at leastone processor of said processor node to maintain designating informationof said at least one element associated with said processor node;computer readable program code which causes said at least one processorof said processor node to determine a nominal node address as an addressfor said processor node for said network; computer readable program codewhich causes said at least one processor of said processor node to sensepresent designating information of at least one element associated withsaid processor node; computer readable program code which causes said atleast one processor of said processor node to compare said presentdesignating information to said maintained designating information;computer readable program code which causes said at least one processorof said processor node to determine whether a match is made between saidcompared said present designating information and said maintaineddesignating information, a failure of said match comprising a nodeaddress failure of said processor node for said network; and computerreadable program code which causes said at least one processor of saidprocessor node to, upon said node address failure of said processor nodefor said network, disable said processor node nominal node address fromsaid network at said at least one interface.